FIG. 1 is a block diagram showing a conventional digital data multiplying circuit. Conventional multiplier 10 comprises an n.times.n multiplier A 12 for multiplying n-bit digital data A with an n-bit digital coefficient Ka, and an n.times.n multiplier B 14 for multiplying n-bit digital data B with an n-bit digital coefficient Kb. Multiplier 10 multiplies the data input via two data buses and two coefficient buses, and respectively outputs the result. As shown in FIG. 1, n.times.n multiplier A 12 multiplies n-bit digital data A with n-bit digital coefficient Ka and outputs the resulting n-bit product Ka.times.A, while n.times.n multiplier B 14 multiplies n-bit digital data B with n-bit digital coefficient Ka and outputs the resulting n-bit product Ka.times.B. Many gates, however, are needed to realize the above-described n.times.n multipliers 12 and 14, which occupies excessive chip area when the multiplier is to be realized by a single chip. Specifically, when a digital signal processor using such a multiplier is to be realized by a single chip, the area used on the chip increases with the number of bits n to be multiplied. As a result, manufacturing cost and power consumption are increased and reliability suffers.
Thus, in the prior art, when a data input to a plurality of n-bit digital data buses is multiplied by a coefficient input to another bus, the number of multipliers needed corresponds to the number of input data buses. Therefore, when the multiplier is realized by a single chip, a large chip area is required. As a result, manufacturing cost and power consumption are increased and the reliability is lowered.